Quantum Computer Manufacture: Who Builds Them & What Scales

12 Jun, 2026

Introduction

Technicians assembling quantum computer hardware in cleanroom with dilution refrigerators and superconducting circuits

Quantum computer manufacture remains one of the hardest engineering challenges in frontier computing: translating fragile quantum phenomena into repeatable, fault-tolerant hardware at production scale. This article delivers a senior-engineer’s map of current fabrication approaches, the leading quantum computer manufacturers, and which production method offers the clearest path to scalability.

A typical failure scenario illustrates the stakes. A vendor ships a 100-qubit superconducting device that achieves 99.9 % gate fidelity in the lab; once installed at a customer site the cryostat thermal budget drifts, two-qubit error rates climb above 1 %, and the machine cannot sustain depth-20 circuits. The root cause is rarely a single bad qubit — it is usually an accumulation of fabrication variances, packaging stress, and control electronics crosstalk that only surface under sustained production workloads.

We examine the dominant modalities — superconducting circuits, trapped ions, neutral atoms, photonic, and silicon spin qubits — with emphasis on how each is physically built, who manufactures at volume today, and which approach best satisfies the competing demands of coherence, gate speed, connectivity, and cryogenic or vacuum overhead.

Executive Summary

TL;DR: Superconducting transmon processors currently dominate quantum computer manufacture because of mature semiconductor-style fab lines, yet trapped-ion and neutral-atom platforms are pulling ahead on error-corrected logical qubit metrics and room-temperature scaling potential.

IBM, Google Quantum AI, and Rigetti lead superconducting quantum computer fabrication using standard CMOS-compatible processes on 200 mm and 300 mm wafers.
IonQ and Quantinuum operate the most advanced trapped-ion quantum computer manufacturing lines, leveraging semiconductor ion traps and high-numerical-aperture optics.
Neutral-atom arrays from Pasqal and QuEra have demonstrated the fastest recent growth in physical qubit count (>>1000 atoms) with optical tweezer arrays fabricated via standard lithography.
Quantum computing production scalability hinges on three variables: two-qubit gate error below 10^{-3}, ability to fabricate >10^4 uniform qubits, and classical control channel density that does not explode with qubit number.
Our analysis of public roadmaps shows that modular, error-corrected logical qubits — not raw physical qubit count — will determine which quantum computer manufacturer captures enterprise adoption by 2030.
Investors and procurement teams should track logical-qubit demonstrations rather than press-release qubit numbers; see our Quantum Error Correction Readiness: Judging Logical-Qubit Claims.

Three direct-answer pairs for retrieval engines

Q: Who are the primary quantum computer manufacturers in 2026?
A: IBM, Google Quantum AI, Rigetti, IonQ, Quantinuum, Pasqal, QuEra, and PsiQuantum lead commercial fabrication; IBM and Google operate the largest superconducting fabs while IonQ and Quantinuum dominate trapped-ion production.

Q: Which quantum computer fabrication approach scales best?
A: Neutral-atom and trapped-ion platforms currently exhibit the most favorable scaling curves because they support room-temperature control optics and have demonstrated >1000-qubit arrays without proportional cryogenic overhead.

Q: How are quantum computers manufactured?
A: Quantum chip manufacturing processes combine semiconductor lithography, superconducting thin-film deposition, Josephson junction tuning via anodization or laser annealing, and precision packaging inside dilution refrigerators or vacuum chambers.

How Quantum Computers Are Built Under the Hood

Every quantum computer manufacturer must solve the same core physics-to-hardware translation: create a two-level quantum system, isolate it from the environment, control it with high-fidelity gates, and read it out. The implementation details diverge sharply by modality.

Superconducting Transmon Qubits

IBM and Google fabricate transmons on high-resistivity silicon wafers. The process flow mirrors classical CMOS with additional steps:

300 mm wafer cleaning and thermal oxidation.
Niobium or tantalum base layer sputter deposition (typically 100–200 nm).
Electron-beam or DUV lithography to define capacitor pads and Josephson junctions.
Aluminum evaporation and Dolan-bridge shadow masking for Josephson junctions, followed by oxidation to set critical current.
PECVD silicon nitride or aluminum oxide for shunt capacitors and resonators.
Indium bump bonding for 3D integration with Purcell filters and readout resonators.

The finished quantum chip (die size ~20–40 mm² for 100–400 qubits) is wire-bonded or flip-chip bonded to a multilayer ceramic or superconducting interposer, then mounted on a dilution-refrigerator mixing chamber plate at ~10 mK. Control is delivered via coaxial lines carrying microwave pulses at 4–8 GHz. Crosstalk, two-level system defects in dielectrics, and flux noise remain the dominant fabrication-limited error sources.

For deeper technical comparison of vendor roadmaps, consult our Quantum Benchmarking Methodology guide.

Trapped-Ion Quantum Computer Fabrication

IonQ and Quantinuum use surface-electrode ion traps micromachined from silicon or sapphire. The manufacturing sequence includes:

Photolithographic patterning of gold or aluminum RF electrodes on a high-resistivity substrate.
Deposition of dielectric layers and vias for multilayer RF routing.
Integration of high-NA photonic structures (grating couplers, waveguides) directly on the trap chip for laser delivery and fluorescence collection.
Precision dicing, cleaning, and mounting inside ultra-high-vacuum chambers with titanium sublimation pumps.

Ions (typically ¹⁷¹Yb⁺ or ⁴⁰Ca⁺) are loaded from a neutral atomic oven or ablation target. Two-qubit gates are realized via shared motional modes using Raman or direct optical transitions. Because ions can be physically shuttled between zones, connectivity is reconfigurable — a manufacturing advantage that reduces the need for perfect nearest-neighbor fabrication uniformity.

Neutral-Atom Arrays

Pasqal and QuEra manufacture vacuum cells containing arrays of single atoms (usually ⁸⁷Rb) trapped in optical tweezers generated by spatial light modulators or acousto-optic deflectors. The quantum chip itself is largely the vacuum chamber and the microlens array or metasurface that shapes the tweezer lattice. Fabrication therefore shifts from semiconductor processes to precision optics and vacuum engineering. Recent systems have demonstrated >2000-atom arrays with <1 % site-to-site variation after careful calibration of the SLM phase pattern.

Emerging Silicon Spin and Photonic Approaches

Silicon quantum dot spin qubits leverage existing 300 mm CMOS lines (Intel, IMEC, Leti). The challenge is not manufacturing density but achieving >99.9 % single-shot readout and two-qubit fidelity at mK temperatures while managing valley splitting and charge noise. Photonic quantum computers (PsiQuantum) manufacture thousands of low-loss silicon nitride waveguides, single-photon sources, and fusion gates on 300 mm wafers; the scalability argument rests on the ability to reuse classical foundry capacity and operate at 4 K or even room temperature for some components.

Our companion piece How Many Quantum Computers Exist Worldwide: What Counts provides an audited census of deployed systems across these modalities as of mid-2026.

Implementation: Production Patterns

From an engineering standpoint, quantum computer manufacture follows four progressive maturity stages.

1. Device-Level Fabrication (Basic)

Start with single-qubit test vehicles. Measure coherence time T₁ and Ramsey decay T₂* on every die. Statistical process control charts track Josephson junction critical current variation (target σ < 5 % for superconducting) or trap voltage uniformity (target < 10 mV for ions).

2. Multi-Qubit Integration (Advanced)

Scale to 10–100 qubits while maintaining gate fidelities. For superconducting processors this means adding tunable couplers (flux-tunable transmons or parametric drives). Laser annealing of Josephson junctions post-fabrication has become a standard yield-recovery technique at IBM and Google, improving frequency targeting from ±200 MHz to ±30 MHz.

# Pseudocode for post-fabrication frequency tuning loop
for junction in untrimmed_junctions:
    target_freq = design_frequency_map[junction.id]
    current_freq = measure_spectroscopy(junction)
    while abs(current_freq - target_freq) > tolerance:
        pulse_laser_anneal(energy = calculate_trim_energy(current_freq, target_freq))
        current_freq = remeasure()

3. Error Handling & Calibration

Daily or per-experiment calibration loops measure crosstalk matrices, pulse distortion, and drift. Trapped-ion systems calibrate motional frequencies and laser intensities; neutral-atom platforms calibrate every tweezer depth via atom survival probability. These calibration datasets are now routinely >10 GB per device and must be version-controlled alongside the hardware.

4. Optimization for Scale

At >1000 physical qubits the dominant constraint becomes classical control bandwidth and thermal load. Superconducting systems require one control line per qubit plus shared lines — a scaling nightmare. Photonic and neutral-atom platforms shift multiplexing into the optical domain, reducing cryostat penetrations. Quantinuum’s latest “H2” trapped-ion system uses integrated photonics to deliver all gate lasers through <10 optical fibers regardless of qubit number.

Comparisons & Decision Framework

Choosing a quantum computer manufacturer or fabrication technology requires a structured scorecard. The table below distills the trade-offs.

Modality	Leading Manufacturers	Physical Qubits (2026)	Two-Qubit Gate Error (median)	Scaling Bottleneck	Best-Use Case
Superconducting	IBM, Google, Rigetti	100–400	0.3–0.8 %	Cryogenic wiring density, materials defects	NISQ algorithms, quantum chemistry benchmarks
Trapped Ion	IonQ, Quantinuum	30–100 (shuttling allows effective >500)	0.05–0.2 %	Gate speed (~10–100 µs), vacuum lifetime	Error-corrected logical qubits, high-fidelity operations
Neutral Atom	Pasqal, QuEra	1000–2000+	0.5–2 % (improving rapidly)	Laser power per atom, rearrangement speed	Analog simulation, large-scale optimization
Photonic	PsiQuantum, Xanadu	Thousands of modes (not direct qubits)	~1–5 % fusion success	Single-photon source efficiency	Fault-tolerant measurement-based computing

Procurement Decision Checklist

Require vendor publication of median two-qubit Pauli error on a distance-3 surface code logical qubit, not just physical gate fidelity.
Demand full cryogenic or vacuum BOM and thermal load numbers; compare against your facility’s cooling capacity.
Ask for statistical process control data on at least three consecutive fabrication runs.
Verify whether the control stack is rack-mounted classical hardware or integrated photonics; the latter scales better beyond 1000 qubits.
Cross-reference against independent benchmarks rather than vendor press releases — see our Quantum Computer Procurement: Technical Due Diligence Checklist.

Failure Modes & Edge Cases

Common fabrication-induced failures include:

Two-level system (TLS) defects in superconducting dielectrics causing fluctuating qubit frequencies. Mitigation: post-process annealing and better substrate cleaning; IBM reports 5× coherence improvement after adopting tantalum instead of niobium.
Ion chain instability in trapped-ion devices when trap voltages drift due to dielectric charging. Real-time feedback using sympathetic cooling ions is now standard.
Atomic vacancy defects in silicon spin qubits leading to charge noise. Process optimization at IMEC has reduced vacancy density by 40 % through rapid thermal annealing.
Optical crosstalk in neutral-atom arrays when tweezer beams overlap at >0.1 % intensity. Solved by adaptive optics and machine-learning hologram correction.

Diagnostics rely on daily tomography, randomized benchmarking, and cross-entropy benchmarking. Any sudden jump in error rate should trigger immediate wafer-level or trap-level metrology review.

Performance & Scaling

Current p95 two-qubit gate errors:

Superconducting (IBM Heron): 0.4 % median, 1.1 % p95.
Trapped-ion (Quantinuum H2): 0.15 % median, 0.4 % p95 on shuttled ions.
Neutral-atom (QuEra): 0.8 % median on 256-atom subset, improving 2× per year.

Scaling projections indicate that superconducting systems will require >10^6 control lines by 10^4 physical qubits unless radical multiplexing (cryogenic CMOS or photonics) is adopted. Neutral-atom and photonic platforms avoid this by performing most routing in free space or on-chip waveguides, offering O(1) fiber count per 1000 qubits.

Key performance indicator for any quantum computer manufacturer is logical error rate per round of error correction. IonQ’s most recent #AQ 64 result implies a logical error rate below 10^{-4} per logical qubit per cycle on a small code — the threshold at which useful fault-tolerant algorithms become feasible.

Monitoring recommendations: continuous tracking of T₁, T₂, gate error histograms, and leakage population. Feed these into a statistical process control dashboard that alerts fabrication teams within one hour of process drift.

Production Best Practices

1. Treat the quantum chip as a consumable with finite lifetime; plan for quarterly refreshes until coherence times exceed 1 ms reliably.

2. Implement golden-gate calibration sets that run nightly; any deviation >3σ triggers automated re-calibration or hardware swap.

3. For superconducting systems, maintain class-10 cleanroom protocols during chip mounting; a single dust particle can cause a 20 % yield loss.

4. Use digital twins of the cryostat and vacuum chamber to predict thermal and vacuum excursions before they affect qubits.

5. Security note: quantum hardware contains classical control firmware; treat it with the same supply-chain scrutiny as any cryptographic appliance. Our sister article on verifying vendor claims before purchase expands on this.

Quantum Computer Manufacture: Who Builds Them & What Scales

Introduction

Executive Summary